OcteVue: Microelectronic Test Structures

Integrated approach to design, test and characterization of test structures for microelectronic technologies

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Contact: mketchen@octevue.com

 Reduce microelectronic technology development and manufacturing costs by

• Obtaining AC learning on power/performance and parametrics with ring oscillator and self-timed pulse techniques using standard low-frequency testers
• Emphasizing M1 testable scribe-line test structures to accelerate development and enable early lot deposition in manufacturing
• Utilizing small addressable arrays in kerf for rapid CV and IV characterization with modest statistics
• Avoiding common errors in design that lead to ambiguous test results

Electrical test structures are an essential ingredient in the development and and maintenance of a successful microfabrication technology at any scale. As microelectronic technologies become more complex and expensive, test structures play a critical role in reducing time to maturity and the cost of development and manufacturing. They can also be an extremely effective mechanism for fabless design houses to use to verify the integrity of the technology services they are obtaining from foundaries

Dr. Ketchen has many years of broad, hands-on experience in the area of microelectronic techologies and experimental design in both semiconductor and supercondoctor arenas. In particular he and collaborators worked with IBM's 180 nm to 32 nm CMOS technology nodes to introduce a range of novel DC and AC test structures into CMOS development and manufacturing at IBM. Key elements of scribe-line test structures for CMOS technology are presented in the book entitled

"Microelectronic Test Structures for CMOS Technology"

A comprehensive guide to serve as a handbook for professional engineers and engineering students engaged in design, test and statistical data analysis for CMOS technology characterization
  Authors: Manjul Bhushan and Mark B. Ketchen
  Springer, published August 2011. Available in hardcover and ebook

Selected Publications:

1. Silicon technology inspired test structures and methodology for SFQ model-to-hardware correlation
Bhushan M, Timmerwilke J, Amparo D, Gibson GW, Ketchen MB (2019).
IEEE Trans Appl Supercond 29:5; DOI: 10.1109/TASC.2019.2898410
2. Addressable arrays implemented with one metal level for MOSFET and resistor variability characterization
Ketchen MB, Bhushan M, Costrini G (2009). Proceedings of the 2009 IEEE international conference on microelectronic test structures, 2009, pp 13-18
3. Ring oscillator technique for MOSFET CV characterization
Bhushan M, Ketchen MB, Cai M, Kim C, (2008). IEEE Trans Semicond Manuf 21:180-185
4. Product representative 'at speed' test structures for CMOS characterization
Ketchen MB, Bhushan M (2006). IBM J Res Dev 50: 451-468
5. Ring oscillator based technique for measuring variability statistics
Bhushan M, Ketchen MB, Polonsky S, Gattiker A (2006). Proceedings of the 2006 IEEE international conference on microelectronic test structures, 2006, pp 87-92. Best paper award
6. High speed test structures for in-line process monitoring and model calibration
Ketchen MB, Bhushan M, Pearson DJ (2005). Proceedings of the 2005 IEEE international conference on microelectronic test structures, 2005, pp 33-38. Best paper award